View 79RC64574_280519.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Advanced 64-bit Microprocessors Product Family
Features
High-performance 64-bit embedded Microprocessor - 250MHz operating frequency - >330 Dhrystone MIPS performance - 300MFLOPS/s floating-point performance - Up to 125 million multiply accumulate per second (MAC/s) - MIPS-IV Instruction Set Architecture (ISA), with integer DSP and 3-operand integer multiply extensions - Limited dual-issue microarchitecture x Compatible with RC4640 and RC32364 DSP extensions - DSP Extensions, for consumer applications - 2-cycle repeat rate, on atomic Multiply-add - Multiply-subtract (MSUB) support, for complex number processing - Count-leading-zero/one support, for string searches and normalization x High-performance on-chip cache subsystem - 32kB, two-set associative instruction cache (I-cache) - 32kB, two-set associative data cache (D-cache) - Write-through and write-back data cache operations - High-performance cache-ops, bandwidth management x I-cache and D-cache locking capability (per line), provides improved real-time support x Joint TLB on-chip, for virtual-to-physical address mapping
x x x
79RC64574TM 79RC64575TM
Big- or Little-endian capability RC5000 compatible memory management - On-chip 48-entry, 96-page TLB, for advanced operating system support - Compatible with major operating systems: Windows(R)CE, VxWorks, and others x Bus compatible with IDT 64-bit microprocessor families - Pipeline runs at 2 to 8 times the bus frequency - Bus speeds to 125MHz - 32-bit bus option, for lower cost systems - Enhanced timing protocol for SyncDRAM systems (compatible with IDT79RC64474/475) x RC64574: - 32-bit SysAd bus, for low-cost systems - Pin compatible with RC4640 and RC64474 - 128-pin QFP package x RC64575: - 64-bit SysAd bus interface - Pin compatible with RC4650 and RC64475 - 208-pin QFP package x Industrial temperature range support x JTAG Boundary Scan Interface x 2.5V operation with 3.3V tolerant I/O
Diagra agram Block Diagram
PLL 64-bit Integer Execution Unit DSP Accelerator RC5000 Dual-Issue Instruction Fetch Unit Primary Cache Controller Compatible System Control Coprocessor 48-entry 96-page TLB
Floating-Point Accelerator
666 MFIOPS IEEE 1284
32kB 2 set-associative Instruction Cache (Lockable)
32kB 2 set-associative Data Cache (Lockable)
64-bit/32-bit RC64474/475 Compatible System Interface ClkIn
Figure 1 RC64574/RC64575 Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 28
2001 Integrated Device Technology, Inc.
December 14, 2001
DSC 5607
79RC64574TM 79RC64575TM
Device Overview1
IDT's 79RC64574/575 processors serve a wide range of performance-critical embedded applications that include high-end internetworking systems, digital set-top boxes, web browsers, color printers, and graphics terminals. The RC64574/575 allow a socket compatible upgrade path for IDT's RC4640/50 and RC64474/475 processors. This unprecedented upgradability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1 range of floating-point; and 4:1 range of DSP performance in a single socket. With special emphasis on system bandwidth, floating- point and DSP operations, the RC64574/575 have been optimized for high-performance applications through the integration of high-performance computational units and a high-performance memory hierarchy. The result is a low-cost CPU that is capable of more than 330 Dhrystone MIPS. Through the RC64574/64575 processors IDT offers: x High-performance upgrade paths to existing embedded customers in the internetworking, office automation and visualization markets. x Significant floating-point performance improvements over currently available, moderately priced MIPS CPUs. x Performance improvements through the use of the MIPS-IV ISA. x High-performance DSP acceleration
Instruction Issue Mechanism
The RC64574 and RC64575 are limited dual-issue super-scalar machines that use a traditional 5-stage integer pipeline, as shown in the pipeline diagram on Page 3. For multi-issue operations, these devices recognize the following two general classes of instructions: x Floating-point ALU x All others Such a broad separation of instruction classes insure that there are no data dependencies to restrict multi-issue performance. As they are brought on-chip, these instruction classes are pre-decoded by the RC64574/575, and the class information is then stored in the instruction cache. Assuming there are no pending resource conflicts, the devices can issue one instruction per class per pipeline clock cycle. However, longer latency resources--in either the floating-point ALU (for example, division or square root instructions) or integer unit (such as multiply)--can restrict the issue of instructions. Note that these processors do not perform out-of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. On dual-issue instruction pairs, there are no alignment restrictions, and the RC64574/575 fetch two instructions from the cache per cycle. Thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, because the instruction cache only performs aligned fetches.
1. Detailed system operation information is provided in the RC64574/RC64575 user's manual.
RISCore4000/RISCore5000 Family of Socket Compatible Processors
32-bit External Bus Processors RC4640
CPU Performance FPA Caches External Bus
64-bit RISCore4000 w/ DSP extensions >350MIPS 89 mflops, single precision only 8kB/8kB, 2-way, lockable by set 32-bit
64-bit External Bus Processors RC4650
64-bit RISCore4000 w/ DSP extensions >350MIPS 89 mflops, single precision only 8kB/8kB, 2-way, lockable by set 32- or 64-bit
RC64474
64-bit RISCore4000 >330MIPS 125 mflops, single and double precision 16kB/16kB, 2-way, lockable by set 32-bit, Superset pin compatible w/RC4640 3.3V 180-250 MHz 128 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 32-bit external bus
RC64574
64-bit RISCore5000 w/ DSP extensions >330MIPS 666 mflops, single and double precision 32kB/32kB, 2-way, lockable by line 32-bit, Superset pin compatible w/RC4640, RC64474 2.5V 200-250 MHz 128 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 32-bit external bus
RC64475
64-bit RISCore4000 >330MIPS 125 mflops, single and double precision 16kB/16kB, 2-way, lockable by set 32-or 64-bit, Superset pin compatible w/ RC4650 3.3V 180-250 MHz 208 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 3264- bit bus option
RC64575
64-bit RISCore5000 w/ DSP extensions >330MIPS 666 mflops, single and double precision 32kB/32kB, 2-way, lockable by line 32-or 64-bit, Superset pin compatible w/ RC4650, RC64475 2.5V 250 MHz 208 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 3264- bit bus option
Voltage Frequencies Packages MMU Key Features
3.3V 100-267 MHz 128 PQFP Base-Bounds Cache locking, on-chip MAC, 32-bit external bus
3.3V 100-267 MHz 208 QFP Base-Bounds Cache locking, on-chip MAC, 32-bit & 64 bit bus option
Table 1 RISCore4000/RISCore5000 Processor Family 2 of 28 December 14, 2001
79RC64574TM 79RC64575TM
Instruction Set Architecture
The RC64574/575 implement a superset of the MIPS-IV 64-bit ISA, including CP1 and CP1X functional units and their instruction set. Both 32- and 64-bit data operations are performed by utilizing thirty-two general purpose 64-bit registers (GPR) that are used for integer operations and address calculation. The complete on-chip floating-point coprocessor (CP1)--which includes a floating-point register file and execution units--forms a "seamless" interface, decoding and executing instructions in parallel with the integer unit. CP1's floating-point execution units support both single and double precision arithmetic--as specified in the IEEE Standard 754-- and are separated into a multiply unit and a combined add/convert/ divide/square root unit. Overlap of multiplies and add/subtract is supported, and the multiplier is partially pipelined, allowing the initiation of a new multiply instruction every fourth pipeline cycle. The floatingpoint register file is made up of thirty-two 64-bit registers. The floatingpoint unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle. The system control coprocessor (CP0) registers are also incorporated on-chip and provide the path through which the virtual memory system's page mapping is examined and changed, exceptions are handled, and any operating mode selections are controlled. A secure user processing environment is provided through the user, supervisor, and kernel operating modes of virtual addressing to system software. Bits in a status register determine which of these modes is used.
Load and branch latencies are minimized by the short pipeline of the RC64574/575, and the caches contain special logic that will allow any combination of loads and stores to execute in back-to-back cycles without requiring pipeline slips or stalls, assuming the operation does not miss in the cache.
Computational Units
The RC64574/575 implement a full, single-cycle 64-bit arithmetic logic unit (ALU), for Integer ALU functions other than multiply and divide. Bypassing is used to support back-to-back ALU operations at the full pipeline rate, without requiring stalls for data dependencies. To allow the longer latency operations to run in parallel with other operations, the Integer Multiply/Divide unit of the RC64574/ 575 is separated from the primary ALU. The pipeline stalls only if an attempt to access the HI or LO registers is made before an operation completes. The Floating-point ALU unit is responsible for all of the CP1/CP1X ALU operations--other than DIV/SQRT operations--and is pipelined to allow a single-cycle repeat rate for single-precision operations. The Floating-point DIV/SQRT unit is separated from the floatingpoint ALU, to ensure that these longer latency operations do not prevent the issue of other floating-point operations. Separate logical units are also provided on the RC64574/575 to implement load, store, and branch operations. Intended to enhance the performance of DSP algorithms such as fast fused multiply-adds, multiply-subtracts and three operand multiply operations, new instructions have been added over and above the MIPS-IV ISA.
Integer Pipeline
The integer instruction execution speed is tabulated--in number of pipeline clocks--as follows:
Operation Load Store MULT/MULTU DMULT/DMULTU DIV/DIVU DDIV/DDIVU MAD/MADU MSUB/MSUBU Other Integer ALU Branch Jump 2 2 4 6 36 68 3 4 1 2 2 Latency 1 1 3 5 36 68 2 3 1 2 2 Repeat
System Interfaces
The RC64575 supports a 64-bit system interface that is pin and bus compatible with the RC4650 and RC64475 system interface. The system interface consists of a 64-bit Address/Data bus with eight paritycheck bits and a 9-bit command bus. During 64-bit operation, RC64575 system address/data (SysAD) transfers are protected with an 8-bit parity check bus, SysADC. When initialized for 32-bit operation, the RC64575's SysAD can be viewed as a 32-bit multiplexed bus that is protected by four parity-check bits. The RC64574 supports a 32-bit system interface that is pin and bus compatible with the RC4640 and RC64474. During 32-bit operation, SysAD transfers are performed on a 32-bit multiplexed bus (SysAD 31:0) that is protected by 4 parity check bits (SysADC 6:0). Writes to external memory--whether they are cache miss writebacks, stores to uncached or write-through addresses--use the on-chip write buffer. The write buffer holds a maximum of four 64-bit addresses and 64-bit data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory updates. Included in the system interface are six handshake signals: RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, and ValidIn*; six interrupt inputs, and a simple timing specification that is capable of trans-
Table 2 Integer Instruction Execution Speed
To insure that the maximum frequency of operation is not limited by the speed of the multiplier unit, a "fast multiply" disable reset mode bit (see Table 2) is featured. When this bit is asserted, each multiply operation shown in Table 1 has its latency and repeat rate increased by one cycle.
3 of 28
December 14, 2001
79RC64574TM 79RC64575TM
ferring data between the processor and memory at a peak rate of 1000MB/sec. A boot-time selectable option to run the system interface as 32-bits wide--using basically the same protocols as the 64-bit system--is also supported. A boot-time mode control interface initializes fundamental processor modes and is a serial interface that operates at a very low frequency (SysClock divided by 256). This low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively, the twenty-or-so bits could be generated by the system interface ASIC or a simple PAL. The boot-time serial stream is shown in Table 3.
Serial Description Bit 0 1:4 Reserved Transmit-datapattern. Bit 4 is MSB Value & Mode Setting
Serial Description Bit 11 TimerIntEn
Value & Mode Setting Timer interrupt settings: 0: Enable Timer Interrupt on Int(5) 1: Disable Timer Interrupt on Int(5)
12
System Interface Interface bus width control settings: Bus Width. 0: 64-bit system interface 1: 32-bit system interface Drv_Out Bit 14 is MSB Slew rate control of the output drivers: 10: 100% strength (fastest) 11: 83% strength 00: 67% strength 01: 50% strength (slowest)
13:14
15:17 Must be set to 0. 64-bit bus width: 0: DDDD 1: DDxDDx 2: DDxxDDxx 3: DxDxDxDx 4: DDxxxDDxxx 5: DDxxxxDDxxxx 6: DxxDxxDxxDxx 7: DDxxxxxxDDxxxxxx 8: DxxxDxxxDxxxDxxx 9-15: Reserved. Must not be selected. 32-bit bus width: 0: WWWWWWWW 1: WWxWWxWWxWWx 2: WWxxWWxxWWxxWWxx 3: WxWxWxWxWxWxWxWx 4: WWxxxWWxxxWWxxxWWxxx 5: WWxxxxWWxxxxWWxxxxWWxxxx 6: WxxWxxWxxWxxWxxWxxWxxWxx 7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx 8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx 9-15: Reserved. Must not be selected.
Write address to From 0 to 7 SysClk cycles: write data delay. 0: AD... 1: AxD... 2: AxxD... 3: AxxxD... 4: AxxxxD... 5: AxxxxxD... 6: AxxxxxxD... 7: AxxxxxxxD... Reserved Extend Multiplication Repeat Rate. User must select `0' Initial setting of the "Fast Multiply" bit. 0: Enable Fast Multiply 1: Do not Enable Fast Multiply Note: For pipeline speeds >250MHz, this bit must be set to `1'.
18 19
20:24 25:26
Reserved System configuration identifier. Reserved
User must select `0' Software visible in processorConfig[21:20] 0: Config[21:20] = Mode Bit [25:26] Must be set to 0. User must select `0'
27:256
Table 3 Boot-time Mode Stream (Page 2 of 2)
5:7
PClock-toSysClk-Ratio. Bit 7 is MSB
0: 2 1: 3 2: 4 3: 5 4: 6 5: 7 6: 8 7: Reserved 0: Little endian 1: Big endian 00: R4400 compatible 01: Reserved 10: Pipelined-Write-Mode 11: Write-Reissue-Mode
8 9:10
Endianness Non-block write Mode. Bit 10 is MSB
The clocking interface allows the CPU to be easily mated with external reference clocks. The CPU input clock is the bus reference clock and can be between 33 and 125MHz. An on-chip phase-lockedloop (PLL) generates the pipeline clock (PClock) through multiplication of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at system reset. This allows the pipeline clock to be implemented at a significantly higher frequency than the system interface clock. The RC64574/575 support both single data (one byte through full CPU bus width) and 8-word block transfers on the SysAD bus. The RC64574/575 implement additional write protocols that double the effective write bandwidth. The write re-issue has a repeat rate of 2 cycles per write. Pipelined writes have the same 2-cycle per write repeat rate, but can issue an additional write after WrRdy* deasserts.
Table 3 Boot-time Mode Stream (Page 1 of 2)
4 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Choosing a 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double word data cycles or 8 single word cycles as well as whether a single data transfer--larger than 4 bytes--must be divided into two smaller transfers. As shown in Table 3, the bus delay can be defined as 0 to 7 SysClock cycles and is activated and controlled through mode bit (17:15) settings selected during the reset initialization sequence. The `000' setting provides the same write operations timing protocol as the RC4640, RC4650, and RC5000 processors. To facilitate discrete interface to SyncDRAM, the RC64574/575 bus interface is enhanced during write cycles with a programmable delay that is inserted between the write address and the write data (for both block and non-block writes). Board-level testing during Run-Time mode is facilitated through the full JTAG boundary scan facility. Five pins--TDI, TDO, TMS, TCK, TRST*--have been incorporated to support the standard JTAG interface. The RC64574/575 devices offer a direct migration path for designs that are based on IDT's RC4640/RC4650 and RC64474/RC64475 processors2, through full pin and socket compatibility. Full 64-bit-family software and bus protocol compatibility ensures the RC64574/575 processors access to an existing market and development infrastructure, allowing quicker time to market.
To lock critical sections of code and/or data into the caches for quick access, a per line "cache locking" feature has been implemented. Once enabled, a cache is said to be locked when a particular piece of code or data is loaded into the cache and that cache location will not be selected later for refill by other data.
Power Management
Executing the WAIT instruction enables the processor to enter Standby mode. The internal clocks will shut down, thus freezing the pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Once in Standby Mode, any interrupt, including the internally generated timer interrupt, will cause the CPU to exit Standby Mode.
Thermal Considerations
The RC64574 is packaged in a 128-pin QFP footprint package and uses a 32-bit external bus, offering the ideal combination of 64-bit processing power and 32-bit low-cost memory systems. The RC64575 is packaged in a 208-pin QFP footprint package and uses the full 64-bit external bus. The RC64575 is ideal for applications requiring 64-bit performance and 64-bit external bandwidth. Both devices are guaranteed in a case temperature range of 0 to +85 C for commercial temperature devices and -40 to +85 C for Industrial temperature devices. Package type, speed (power) of the device, and air flow conditions affect the equivalent ambient temperature conditions that will meet these specifications. Using the thermal resistance from case to ambient (CA) of the given package, the equivalent allowable ambient temperature, TA, can be calculated. The following equation relates ambient and case temperatures: TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various air flow are shown in Table 4. Note that the RC64574/575 processor implements advanced power management, which substantially reduces the typical power dissipation of the device. CA
Airflow (ft/min) 128 QFP 208 QFP 0 16 20 200 10 13 400 9 10 600 7 9 800 6 8 1000 5 7
Development Tools
An array of hardware and software tools is available to assist system designers in the rapid development of RC64574/575 based systems. This accessibility allows a wide variety of customers to take full advantage of the device's high-performance features while addressing today's aggressive time-to-market demands.
Cache Memory
To keep the high-performance pipeline of the RC64574/575 full and operating efficiently, on-chip instruction and data caches have been incorporated. Each cache has its own data path and can be accessed in the same single pipeline clock cycle. The 32kB two-way set associative instruction cache is virtually indexed, physically tagged, and word parity protected. Because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing both operations to occur simultaneously. The instruction cache provides a peak instruction bandwidth of 2GB/sec at 250MHz. The 32kB two-way set associative data cache is byte parity protected and has a fixed 32-byte (eight words) line size. Its tag is protected with a single parity bit. To allow simultaneous address translation and data cache access, the D-cache is virtually indexed and physically tagged. The data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 2GB/s.
2.
Table 4 Thermal Resistance (CA) at Various Airflows
Revision History
July 22, 1999: Original data sheet.
To ensure socket compatibility, refer to Table 8 and Table 9.
5 of 28
December 14, 2001
79RC64574TM 79RC64575TM
September 9, 1999: Made several changes in JTAG Interface section of Table 5. Added information on Pin 63 in Table 5. October 14, 1999: Revised data in the Power Consumption tables for RC64574 and RC64575. November 16, 1999: Added Power Curve graphs, revised data in System Interface Parameters table, added System Clock Jitter row to Clock Parameter table. December 20, 1999: Table 7 "RC64574 128-Pin Package" on page 12, Changed pin #75 function from Vcc to N.C. March 7, 2000: In Table 1, added "with DSP extensions" in the CPU row under RC64574 and RC64575 columns and changed "by set" to "by line" in the Caches row for RC64574 and RC64575 columns. Added rows in the Data Output and Data Output Hold rows in the System Interface Parameters table. Removed references to 300 MHz, and changed bandwidth speed to 2GB/second in Cache Memory section. Revised Power Curves. March 28, 2000: Replaced existing figure in Mode Configuration Interface Reset Sequence section with 3 reset figures. Revised values for 250MHz in System Interface Parameters table. Changed Data Sheet from Preliminary to final. April 3, 2000: Deleted signal tDZ from Figure 6. April 25, 2001: In the Absolute Maximum Ratings table, changed upper voltage limit from 3.8 to 4.0V and removed "Vin should not exceed Vcc +0.5 volts" from footnote #1. In DC Electrical Characteristics table, changed maximum value for Vih from 3.3 to 3.8V for all speeds. May 1, 2001: In the Data Output Hold category of the System Interface Parameters table, changed values in the Min column for all speeds from 1.0 to 0. In the Electrical Characteristics table, values were added to the System Clock Jitter row. Added Industrial temperature range of -40 C to +85 C. December 14, 2001: In Absolute Maximum Ratings Table, changed the Industrial low-end temperature for symbol Tc to read -40 degrees instead of 0 degrees.
6 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Pin Description Table
The following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.
Pin Name System Interface ExtRqst* I External request An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request by asserting Release*. Release interface In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals to the requesting device that the system interface is available. Read Ready The external agent asserts RdRdy* to indicate that it can accept a processor read request. Write Ready An external agent asserts WrRdy* when it can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid Output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. In 64 bit interface mode, during address phases only, SysAd(35:0) contains invalid address information. The remaining SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer phase. For all double-word accesses (read or write), the low-order 3 bits (SysAD[2:0]) will always be output as zero during the address phase. In 32-bit interface mode and in the RC64574, SysAD(63:32) is not used, regardless of Endianness. A 32-bit address and data communication between processor and external agent is performed via SysAD(31:0). System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for SysAD(31:0). System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command Parity A single, even-parity bit for the Syscmd bus. This signal is always driven low. Type Description
Release*
O
RdRdy* WrRdy* ValidIn*
I I I
ValidOut*
O
SysAD(63:0)
I/O
SysADC(7:0)
I/O
SysCmd(8:0) SysCmdP
I/O I/O
Clock/Control Interface SysClock I SystemClock The system clock input establishes the processor and bus operating frequency. It is multiplied internally by 2,3,4,5,6,7, or 8 to generate the pipeline clock (PClock). Quiet VCC for PLL Quiet VCC for the internal phase locked loop. Quiet VSS for PLL Quiet VSS for the internal phase locked loop. Table 5 Pin Descriptions (Page 1 of 2)
VCCP VSSP
I I
7 of 28
December 14, 2001
79RC64574TM 79RC64575TM Pin Name Interrupt Interface Int*(5:0) NMI* Initialization Interface VCCOk I VCC is OK When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization sequence. Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. Boot-mode clock Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six. Boot-mode data in Serial boot-mode data input. I I Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register. Type Description
ColdReset*
I
Reset*
I
ModeClock ModeIn JTAG Interface TDI
O I
I
JTAG Data In On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register, depending on the TAP controller state. An external pull-up resistor is required. JTAG Data Out On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When no data is shifted out, the TDO is tri-stated (high impedance). JTAG Clock Input An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the system and processor clock with nominal 40-60% duty cycle. JTAG Command Select The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising edge of TCK. An external pull-up resistor is required. JTAG Reset The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the processor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this active low pin. When asserted low, this pin will also tristate the TDO pin. An external pull-down resistor is required. JTAG 32-bit scan This pin is used to control length of the scan chain for SysAD (32-bit or 64-bit) for the JTAG mode. When set to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in pull-down device to guarantee 32-bit scan, if it is left un connected. JTAG VCC This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset. Table 5 Pin Descriptions (Page 2 of 2)
TDO
O
TCK
I
TMS
I
TRST*
I
JTAG32*
I
JR_Vcc
I
8 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Logic Diagram -- RC64574/RC64575
Figure 1 illustrates the direction and functional groupings for the processor signals.
Clock/Control Interface
SysClock VCCP VSSP
64 8
9
SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP
TDI Interface TDO TMS TRST* JTAG TCK JTag32* JR_Vcc RdRdy*
Initialization
RC64574/ RC64575 Logic Symbol
VCCOK ColdReset* Reset* ModeClock ModeIn
System Interface
December 14, 2001
6
ExtRqst* Handshake Signals Release* ValidIn* ValidOut*
Int*(5:0)
Figure 1 Logic Symbol for RC64574/RC64575
9 of 28
Interrupt Interface
WrRdy*
NMI*
Interface
79RC64574TM 79RC64575TM
RC64575 208-pin QFP Package Pin-out
Pin names followed by an asterisk (*) are active when low. For maximum flexibility and compatibility with future designs, N.C. pins should be left floating.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Function N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD11 Vss Vcc SysCmd8 SysAD42 SysAD10 SysCmd7 Vss Vcc SysAD41 SysAD9 SysCmd6 SysAD40 Vss Vcc SysAD8 SysCmd5 SysADC4 SysADC0 Vss Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Function JTAG32* N.C. N.C. N.C. SysCmd2 SysAD36 SysAD4 SysCmd1 Vss Vcc SysAD35 SysAD3 SysCmd0 SysAD34 Vss Vcc SysAD2 Int5* SysAD33 SysAD1 Vss Vcc Int4* SysAD32 SysAD0 Int3* Vss Vcc Int2* SysAD16 SysAD48 Int1* Vss Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Function N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD52 ExtRqst* Vcc Vss SysAD21 SysAD53 RdRdy* Modein SysAD22 SysAD54 Vcc Vss Release* SysAD23 SysAD55 NMI* Vcc Vss SysADC2 SysADC6 SysAD24 Vcc Vss SysAD56 Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Function N.C. N.C. SysAD59 ColdReset* SysAD28 Vcc Vss SysAD60 Reset* SysAD29 SysAD61 SysAD30 Vcc Vss SysAD62 SysAD31 SysAD63 Vcc Vss
VccOK
SysADC3 SysADC7 N.C. TDI TRst* TCK TMS TDO
VccP VssP
SysClock Vcc Vss
Vcc
SysCmd4 SysAD39 SysAD7
Table 6 RC64575 208-pin QFP Package Pin-Out (Page 1 of 2)
10 of 28
December 14, 2001
79RC64574TM 79RC64575TM Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function SysCmd3 Vss Vcc SysAD38 SysAD6 ModeClock WrRdy* SysAD37 SysAD5 Vss Vcc N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Pin 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function Vcc SysAD17 SysAD49 Int0* SysAD18 Vss Vcc SysAD50 ValidIn* SysAD19 SysAD51 Vss Vcc ValidOut* SysAD20 N.C. N.C. N.C. N.C. Pin 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function SysAD25 SysAD57 Vcc Vss N.C SysAD26 SysAD58 N.C. Vcc Vss SysAD27 N.C. JR_Vcc N.C. N.C. N.C. N.C. N.C. N.C. Pin 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function SysADC5 SysADC1 Vcc Vss SysAD47 SysAD15 SysAD46 Vcc Vss SysAD14 SysAD45 SysAD13 SysAD44 Vss Vcc SysAD12 SysCmdP SysAD43 N.C.
Table 6 RC64575 208-pin QFP Package Pin-Out (Page 2 of 2)
11 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64574 128-pin Package Pin-out
N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active when low.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function JTAG32* SysCmd2 Vcc Vss SysAD5 WrRdy* ModeClock SysAD6 Vcc Vss SysCmd3 SysAD7 SysCmd4 Vcc Vss SysADC0 SysCmd5 SysAD8 Vcc Vss SysCmd6 SysAD9 Vcc Vss SysCmd7 SysAD10 SysCmd8 Vcc Vss SysAD11 SysCmdP SysAD12 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Vcc Vss SysAD13 SysAD14 Vss Vcc SysAD15 Vss Vcc SysADC1 Vss Vcc SysClock VssP VccP TDO TMS TCK TRst* TDI Vss SysADC3 VccOK Vss Vcc SysAD31 Vss Vcc SysAD30 SysAD29 Reset* Vss Function Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Vcc SysAD28 ColdReset* SysAD27 Vss Vcc JR_Vcc SysAD26 N.C. Vss N.C. SysAD25 Vss Vcc SysAD24 SysADC2 Vss Vcc NMI* SysAD23 Release* Vss Vcc SysAD22 Modein RdRdy* SysAD21 Vss Vcc ExtRqst* SysAD20 ValidOut* Function Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Vcc Vss SysAD19 ValidIn* Vcc Vss SysAD18 Int0* SysAD17 Vcc Vss Int1* SysAD16 Int2* Vcc Vss Int3* SysAD0 Int4* Vcc Vss SysAD1 Int5* SysAD2 Vcc Vss SysCmd0 SysAD3 Vcc Vss SysCmd1 SysAD4 Function
Table 7 RC64574 128-Pin Package
12 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64574 Socket Compatibility to RC64474 & RC4640
The RC64574/575 is 100% pin compatible with the RC64474/475 with the supply voltage being the only difference. RC64474/475 requires a 3.3V supply, while RC64574/575 requires a 2.5V supply. To ensure socket compatibility between the RC64574/RC64474 and the RC4640 devices, several pin changes are required, as shown in the tables below. Note: The RC64574/575 are 2.5V parts and as such all Vcc must be at the correct voltage for a given part.
Pin 1 48 49 50 51 52 71 RC4640 N.C Vss Vss Vss Vss Vss N.C. RC64574/ RC64474 JTAG32* TDO TMS TCK TRst* TDI JR_Vcc Compatible to RV4640? Yes Yes Yes Yes Yes Yes Yes Comments Pin has an internal pull-down, to enable 32-bit scan. Can also be left a N.C. Can be driven with Vss, if JTAG is not needed. Is tristated when TRst* is low. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be left N.C. in RC64574, if JTAG is not need. If JTAG is needed, it must be driven to Vcc.
Table 8 RC64574 Socket Compatibility to RC64474 and R4640
RC64575 Socket Compatibility to RC64475 & RC4650
RV4650 32-bit N.C. RC64575 32-bit RC64475 32-bit JTAG32* RV4650 64-bit No Connect RC64575 64-bit RC64475 64-bit JTAG32* Compatible to RV4650? Yes
Pin
Comments
53
In 32-bit, this pin can be left unconnected because of internal pull-down. In 64-bit, this assumes that JTAG will not be used. If using JTAG, this pin must be at Vcc. In RC64475, can be left a N.C, if JTAG is not need. If JTAG is needed, it must be driven to Vcc. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C.
150
N.C.
JR_Vcc
No Connect
JR_Vcc
Yes
180 181 182 183 184
N.C. N.C. N.C. N.C. N.C.
TDI TRsT* TCK TMS TDO
No Connect No Connect No Connect No Connect No Connect
TDO TRsT* TCK TMS TDIO
Yes Yes Yes Yes Yes
Table 9 RC64575 Socket Compatibility to RC64475 & RC4650
13 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Absolute Maximum Ratings
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol VTERM TC TBIAS TSTG IIN IOUT
1. 2.
Rating Terminal Voltage with respect to GND Operating Temperature (case)
Commercial (2.5V5%) -0.51 to +4.0 0 to +85 -55 to +125 -55 to +125 203 504
Industrial (2.5V5%) -0.51 to +4.0 -40 to +85 -55 to +125 -55 to +125 203 504
Unit V C C C mA mA
2
Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current
VIn minimum = -2.0V for pulse width less than 15ns. For 3.3V tolerant input, VIn maximum is 3.8V. Case temperature when device is powered up but not operating. VIN < 0V or VIN > VCC. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
3. When 4.
Recommended Operation Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +85C (Case) -40C to + 85C (Case) GND 0V 0V RC64574/575
Vcc
2.5V5% 2.5V5%
DC Electrical Characteristics
Commercial Temperature Range--RC64574/575 (Tcase = 0C to +85C Commercial, Tcase = -40C to +85C Industrial, Vcc = 2.5V 5%)
RC64574/RC64575 200MHz Min VOL VOH VOL VOH VIL VIH IIN CIN -- Vcc - 0.1V -- 2.0V -0.5V 0.7 Vcc -- -- Max 0.1V -- 0.4V -- 0.2Vcc 3.8V 10uA 10pF -- Vcc - 0.1V -- 2.0V -0.5V 0.7 Vcc -- -- RC64574/RC64575 250MHz Min Max 0.1V -- 0.4V -- 0.2Vcc 3.8V 10uA 10pF -- -- 0 VIN VCC -- |IOUT|= 4mA |IOUT|= 20uA
Parameter
Conditions
14 of 28
December 14, 2001
79RC64574TM 79RC64575TM RC64574/RC64575 200MHz Min CIO Cclk I/OLEAK -- -- -- Max 10pF 10pF 20uA -- -- -- RC64574/RC64575 250MHz Min Max 10pF 10pF 20uA Input/Output Leakage --
Parameter
Conditions
Power Consumption--RC64574 Note: The following table assumes as 4:1 pipeline to bus clock ratio.
Parameter ICC stand-by RC64574 200MHz Typical1 -- -- active 470 mA2 Max 60 mA2 120 mA2 550 mA2 RC64574 250MHz Typical1 -- -- 550 mA2 Max 60 mA2 120 mA2 680 mA2 Conditions CL = 0pF3 CL = 50pF CL = 0pF No SysAd activity3 Vcc = 2.63V CL = 50pF R4x00 compatible writes, TC = 25oC Vcc = 2.63V CL = 50pF Pipelined writes or write re-issue, TC = 25oC3 Vcc = 2.63V
reference only.
550mA2
650 mA2
650 mA2
800 mA2
600 mA2
715 mA4
715 mA2
880 mA4
1.
Typical integer instruction mix and cache miss rates. Guaranteed by design. These are the specifications IDT tests to insure compliance.
2. These are not tested. They are the results of engineering analysis and are provided for 3. 4.
RC64574 Power Curves The following two graphs contain power curves that show power consumption at various bus frequencies. Power consumption is based on the values for R4x00 compatible write mode, shown in the table above. Note: Only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported.
15 of 28
December 14, 2001
79RC64574TM 79RC64575TM
1000 900 800 700 600 500 400 300 200 100 20
Typical Power (mA)
3x 5x 6x 7x 4x
2x
2x Mode 3x Mode 4x Mode 5x Mode 6x Mode 7x Mode
40
60
80
100
120
System Bus Speed (MHz)
Figure 2 Typical Power Usage - RC64574
1100 1000 900 800 700 600 500 400 300 200 20
Maximum Power (mA)
3x 5x 6x 7x 4x
2x
2x Mode 3x Mode 4x Mode 5x Mode 6x Mode 7x Mode
40
60
80
100
120
System Bus Speed (MHz)
Figure 3 Maximum Power Usage - RC64574
16 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Power Consumption--RC64575 Note: The following table assumes a 4:1 pipeline to bus clock ratio.
Parameter ICC stand-by RC64575 200MHz Typical1 -- -- active, 64-bit bus option4 510 mA2 Max 60 mA2 120 m2A 680 mA2 RC64575 250MHz Typical1 -- -- 600 mA2 Max 60 mA2 120 m2A 810 mA2 CL = 0pF3 CL = 50pF CL = 0pF No SysAd activity3 Vcc = 2.63V CL = 50pF R4x00 compatible writes, TC = 25oC Vcc = 2.63V CL = 50pF Pipelined writes or write re-issue, TC = 25oC3 Vcc = 2.63V Conditions
600 mA2
800 mA2
700 mA2
950 mA2
660 mA2
880 mA5
770 mA2
1050 mA5
1. 2.
Typical integer instruction mix and cache miss rates. These are not tested. They are the results of engineering analysis and are provided for reference only. design. In 32-bit bus option, use RC64574 power consumption values. These are the specifications IDT tests to insure compliance.
3. Guaranteed by 4. 5.
RC64575 Power Curves The following two graphs contain power curves that show power consumption at various bus frequencies. Power consumption is based on the values for R4x00 compatible write mode, shown in the table above. Note: Only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported.
1100 Typical Power (mA) 3x 900 700 7x 500 300 100 20 40 60 80 100 120 System Bus Speed (MHz)
Figure 4 Typical Power Usage - RC64575
2x
2x Mode 3x Mode 4x Mode 5x Mode 6x Mode 7x Mode
5x 6x
4x
17 of 28
December 14, 2001
79RC64574TM 79RC64575TM
1400 Maximum Power (mA) 1200 1000 800 600 400 200 20 40 60 80 100 120 System Bus Speed (MHz)
Figure 5 Maximum Power Usage - RC64575
5x 7x 6x 4x
3x
2x
2x Mode 3x Mode 4x Mode 5x Mode 6x Mode 7x Mode
18 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Timing Characteristics--RC64574/RC64575
Cycle SysClock tSysClk tSysClkLow tSysClkP 1 2 3 4
SysAD,SysCmd Driven SysADC
D tDO
D tDOH
D
SysAD,SysCmd Received SysADC
D tDS tDH
D
D
D
Control Signal CPU driven ValidOut* Release* Control Signal CPU received RdRdy* WrRdy* ExtRqst* ValidIn* NMI* Int*(5:0)
* = active low signal
tDO tDOH
tDS
tDH
Figure 6 System Clocks Data Setup, Output, and Hold Timing
t TC K TCK t3 t1 t2 t5
TD I/ TMS tD S TD O TD O tD O
Notes to diagram: t1 = tTCKlow t2 = tTCKHIGH t3 = tTCKFALL t4 = TRST (reset pulse width) t5 = tTCKRise
tD H TDO
TRST*
t4
> = 25 ns
Figure 7 Standard JTAG Timing
19 of 28
December 14, 2001
79RC64574TM 79RC64575TM
System Interface Parameters
RC64574/ RC64575 200MHz Min Data Output tDO = Max mode14..13 = 10 (Fastest) mode14..13 = 11 (85%) mode14..13 = 00 (66%) mode14..13 = 01 (Slowest) Data Output Hold tDOH1 mode14..13 = 10 mode14..13 = 11 mode14..13 = 00 mode14..13 = 01 Data Input
1. 50 pf loading
Parameter
Symbol
Test Conditions
RC64574/ RC64575 250MHz Min -- -- -- -- 0 0 0 0 2 1.0 Max 4.3 4.5 5 5 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns Units
Max 5 6 7 8 -- -- -- -- -- --
-- -- -- -- 0 0 0 0 2 1.0
tDS tDH
on external output signals
trise = 3ns tfall = 3ns
Boot-time Interface Parameters
RC64574/ RC64575 200MHz Min Mode Data Setup tDS Mode Data Hold tDH -- -- 4 0 Max -- -- 4 0 RC64574/ RC64575 250MHz Min Max -- -- SysClock Cycle SysClock Cycle Conditions
Parameter
Symbol
Test Conditions
20 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Sequence Mode Configuration Interface Reset Sequence
Vcc
MasterClock
2.3V 2.3V
(MClk)
> 100ms
TDS 256 MClk cycles 256 MClk cycles
VCCOK
ModeClock TMDS TMDH Bit 0 TDS ColdReset* TDS > 64K MClk cycles > 64 MClk cycles TDS Bit 1 Bit 255 TDS
ModeIn
Reset*
Figure 8 Power-on Reset
Vcc
Master Clock
(MClk)
TDS > 100ms VCCOK
TDS 256 MClk cycles 256 MClk cycles
ModeClock TMDS Bit 0 TDS ColdReset* TDS > 64K MClk cycles > 64 MClk cycles TDS TMDH Bit Bit 1 255 TDS
ModeIn
Reset*
Figure 9 Cold Reset
Vcc
Master Clock
(MClk)
VCCOK 256 MClk cycles
ModeClock
ModeIn
ColdReset* TDS TDS > 64 MClk cycles
Reset*
Figure 10 Warm Reset
21 of 28
December 14, 2001
79RC64574TM 79RC64575TM
AC Electrical Characteristics
(Tcase = 0C to +85C Commercial, Tcase = -40C to +85C Industrial, Vcc = 2.5V 5%) Clock Parameters--RC64574/575
Test Conditions -- Transition 3ns Transition 3ns -- -- -- -- -- -- -- -- -- -- --
and 90%
Parameter
Symbol
RC64574/RC64575 200MHz Min 100 3 3 33 10 -- -- -- -- -- -- -- -- -- 200 -- -- 100 30 + 250 2 2 256 tSCP 100 40 40 5 5 Max
RC64574/RC64575 250MHz Min 100 3 3 33 8 -- -- -- -- -- -- -- -- -- 250 -- -- 125 30 + 250 2 2 256 tSCP 100 40 40 5 5 Max
Units
Pipeline Clock Frequency System Clock HIGH System Clock LOW System Clock Frequency System Clock Period System Clock Jitter System Clock Rise Time1 System Clock Fall Time1 ModeClock Period JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time
PCLk tSCHIGH tSCLOW
--
MHz ns ns MHz ns ps ns ns ns ns ns ns ns ns
tSCP tJITTER tSCRise tSCFall tModeCKP tTCK tTCKHIGH tTCKLOW tTCKRise tTCKFall
1. Rise and Fall times are measured between 10%
Capacitive Load Deration--RC64574/575
Parameter Load Derate Symbol CLD Test Conditions -- 200MHz Min -- Max 2 250MHz Min -- Max 2 Units ns/25pF
Output Loading for AC Testing
VREF
+1.5V
- + CLD
To Device Under Test
Signal All Signals 50 pF
Cld
22 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64575 208-pin Package Diagram
The RC64575 is available in a 208-pin QFP package.
23 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64575 208-pin Package Diagram (page2)
24 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64574 128-pin Package Diagram (page 1 of 3)
The RC64574 is available in a 128-pin QFP package.
25 of 28
December 14, 2001
79RC64574TM 79RC64575TM
3) RC64574 128-pin Package Diagram (page 2 of 3)
26 of 28
December 14, 2001
79RC64574TM 79RC64575TM
RC64574 128-pin Package Diagram (page 3 of 3)
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
for Tech Support: email: rischelp@idt.com phone: 408-492-8208
27 of 28
December 14, 2001
79RC64574TM 79RC64575TM
Ordering Information
IDT79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package
Valid Combinations
IDT79RC64T574 - 200, 250, DZ IDT79RC64T575 - 200, 250, DP IDT79RC64T574 - 200, 250, DZI IDT79RC64T575 - 200, 250, DPI
128-pin QFP package, Commercia
208-pin QFP package, Commercia
128-pin QFP package, Industrial T
08-pin QFP package, Industrial Te
28 of 28
December 14, 2001

▲Up To Search▲

Price & Availability of 79RC64574

	To Download 79RC64574 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .